1. Field of the Invention
This invention relates to the field of memory devices, and more specifically, to a method and apparatus for detecting and locating resistive defects in the wordlines of memories.
2. Background Information
In memory devices, for example SRAM, DRAM, etc. it is a common practice to run wordlines using polysilicon. However, because polysilicon intrinsically has a high resistance, on the order of approximately 50-500ohms per square (.OMEGA./sq), many manufacturers combined the polysilicon with a cladding layer. Cladding layers 120 are generally formed above the polysilicon layer 110 and run parallel to the polysilicon layer, as is illustrated in FIG. 1a. Cladding layers 120 may be made of materials, such as, titanium silicide, tungsten, cobalt silicide, and other lower resistance materials. Because the cladding layer is generally made up of a lower resistance material, the combined polysilicon with cladding layer may have a resistance on the order of approximately 3-10 ohms per square (.OMEGA./sq). Thus, the combined polysilicon with cladding layer wordline 100 has a significantly lower resistance than that of just polysilicon wordlines.
A problem that occurs, however in the combined polysilicon with cladding layer designs is that cracks, breaks, or other defects may be formed in the polysilicon layer, in the cladding layer, or both. A defect increases the resistance in the wordline, slowing down the functioning of the memory, and thus impairs the frequency operation of the memory device. Since the resistance of the polysilicon layer is already high and because the cladding layer (which has a lower resistance) may be used to bypass the polysilicon layer, a defect 130 in the polysilicon layer (as illustrated in FIG. 1b) may slow down a memory array on the order of a few nanoseconds. A few nanoseconds in current memory technology is not a significant amount of time, however, in future generations of memory technology this could become a crucial amount of time. Currently however, one of the main concerns in memory technology is with defects that occur in the cladding layer.
Recall that the cladding layer is made of a lower resistance material and is used to offset the significantly higher resistance of the polysilicon layer. A defect 140 in the cladding layer increases the resistance of the cladding layer and may cause the use of the higher resistance polysilicon layer to bypass the defect in the cladding layer (as is illustrated in FIG. 1c). Thus, a defect in the cladding layer may cause a part to slow down fractions of nanoseconds for minor defects to several microseconds for severe defects. The extra resistance caused by the defect 140 in the cladding layer translates into delay which substantially slows down the part.
Another problem, which stems from the problem of defects slowing down a memory device, is the detection of such defects during testing. When testing a part for defects, defects which form an open in the wordline can be detected because they disable at least a portion of the memory device. Defects, such as those described above with respect to the cladding layer and polysilicon layer, do not completely disable a portion of the memory device. Rather, such defects only slow the device down. Current methods for testing memory devices are only able to detect defects which disable a portion of the memory device and are unable to detect defects which only slow the device down.
Testing memory devices requires the use of complex test patterns. Memories are made up of bits which are arranged in an array format using rows and columns. The bits in the memory array are densely packed in order to follow the trend toward the minimum design rule. A typical memory array may be made up of millions and billions of bits. Thus, in order to test these arrays for defects exhaustive memory test patterns have to be conducted. FIG. 2 illustrates a simplified example of a memory array 200. Memory array 200 is made up of wordlines 210 that correspond to rows 250. Wordlines 210 are made up of bits (not shown) that correspond to columns 260. Thus, to access a particular bit in memory array 200, the wordline 210 is selected by row and the bit in that wordline is selected by column.
One such prior art test, which is considered the most simplistic, is to read and write to every bit of the memory array. Reading and writing to every bit tests each bit for functionality. Such a test technique sounds easy enough, however, a simple memory array may have millions of bits. Testing in this simple manner only allows the detection of the simplest types of defects. Some defects are very difficult to detect and if they escape detection they may potentially cause failures later in the life of the device.
Another prior art test, commonly called the "butterfly", reads and writes to several bits of the memory array. The butterfly technique reads 330 to a single bit 311 in a memory array 300 (as illustrated in FIG. 3a), writes 340 to the bits (312, 313, 314, and 315) which surround bit 311 (as is illustrated in FIG. 3b), and then reads 330 the bit 311 again (as is illustrated in FIG. 3c). This process is repeated in several patterns over the memory array. For example, the butterfly technique may start in the upper left hand corner of the array 300 and work horizontally across the rows and then down the columns to the next row (as illustrated in FIG. 3d), then the technique may work vertically down the column and across the row to the next column (as illustrated in FIG. 3e), and then the technique may work diagonally across the memory array (as illustrated in FIG. 3f). By testing the array in different fashions (i.e. horizontally, vertically, and diagonally) each of these testing fashions may find some subset of problems within the memory array that enables the detection of a defect.
Other prior art tests using various testing patterns and functions are also available, but still exhibit similar problems to the two examples given above. Among these problems is the fact that these prior art tests are slow. Testing each bit individually or testing a complex pattern of bits in a memory device that is made up of millions of bits is extremely time consuming.
Another problem associated with the testing techniques described above is that they just test whether or not the device is working. These prior art techniques do not test whether or not the memory device is functioning at the appropriate frequency or speed. This is due in large part to the types of testers which are currently available. Presently available testers test memory devices at much slower speeds (or frequencies) than the devices actually run. Since these testers test memory devices at lower frequencies they are unable to determine if the memory device is capable of functioning at its appropriate frequency. Thus, the only defects detectable using current testing techniques are those defects which affect whether or not the memory device works. In other words, only those defects which disable a portion of the memory device may be detected. Therefore, in the example described above wherein the defect is in the cladding layer of the wordline and the device still works but at a lower frequency, the defect would not be detected using such prior art testing techniques.
Testers which have the ability to run such complex memory test patterns at high frequencies and have the ability to detect small performance variations between devices are expensive and hard to find. Even if such higher frequency testers were readily available they would be so outrageously expensive that their cost would be prohibitive of their use.
An additional problem with current memory array testing techniques at very high frequency is that these testing techniques are unable to determine the location of defect(s) within the memory array. It is important to determine the location of the defect in order to address how the defect occurred. For example, if the location of the defect is known, a manufacturer may look to the processing steps used to create that portion of the memory array. If it is determined that an error in the processing steps created the defect, then that error may be corrected in the future when manufacturing such memory arrays.
Thus, what is needed is a method and apparatus for detecting defects that not only has the ability to detect defects that disable a portion of the memory device, but also has the ability to detect defects that lower the frequency of the memory device. It would also be advantageous if such a method and apparatus had the capability of determining the location of such defects in the wordlines of memory arrays.